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ITC
1996
IEEE
127views Hardware» more  ITC 1996»
15 years 10 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey
ICCAD
1994
IEEE
76views Hardware» more  ICCAD 1994»
15 years 10 months ago
An efficient procedure for the synthesis of fast self-testable controller structures
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
Sybille Hellebrand, Hans-Joachim Wunderlich
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
15 years 10 months ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
ASWEC
2008
IEEE
15 years 8 months ago
Root Cause Analysis Using Sequence Alignment and Latent Semantic Indexing
Automatic identification of software faults has enormous practical significance. This requires characterizing program execution behavior. Equally important is the aspect of diagno...
R. P. Jagadeesh Chandra Bose, U. Suresh
FLAIRS
2004
15 years 8 months ago
Backcalculation of Airport Flexible Pavement Non-Linear Moduli Using Artificial Neural Networks
The Heavy Weight Deflectometer (HWD) test is one of the most widely used tests for assessing the structural integrity of airport pavements in a non-destructive manner. The elastic...
Kasthurirangan Gopalakrishnan, Marshall R. Thompso...