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» Evolutionary Computation in Structural Design
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DAC
2009
ACM
16 years 7 months ago
Spare-cell-aware multilevel analytical placement
Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validatio...
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yu...
DAC
2007
ACM
16 years 7 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
DAC
2007
ACM
16 years 7 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
DAC
2002
ACM
16 years 7 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
DAC
2002
ACM
16 years 7 months ago
A flexible accelerator for layer 7 networking applications
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
Gokhan Memik, William H. Mangione-Smith