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» Evolutionary Computation in Structural Design
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CCGRID
2010
IEEE
15 years 5 months ago
An Adaptive Data Prefetcher for High-Performance Processors
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
Yong Chen, Huaiyu Zhu, Xian-He Sun
JCISE
2002
128views more  JCISE 2002»
15 years 6 months ago
A Collaborative Framework for Integrated Part and Assembly Modeling
An ideal product modeling system should support both part modeling and assembly modeling, instead of just either of them as is the case in most current CAD systems. A good basis f...
Rafael Bidarra, Niels Kranendonk, Alex Noort, Will...
DAC
2000
ACM
16 years 7 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
16 years 7 days ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
ACL
2004
15 years 8 months ago
Balancing Clarity and Efficiency in Typed Feature Logic Through Delaying
The purpose of this paper is to re-examine the balance between clarity and efficiency in HPSG design, with particular reference to the design decisions made in the English Resourc...
Gerald Penn