This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and f...
Paul Z. Kolano, Richard A. Kemmerer, Dino Mandriol...
: Large Critical Complex Infrastructures are increasingly dependent on IP networks. Reliability by redundancy and tolerance are an imperative for such dependable networks. In order...
Tobias Chyssler, Stefan Burschka, Michael Semling,...
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
We consider a code-spread and chip-interleaved time-hopping (TH) multiple-access scheme for multiuser ultra-wideband (UWB) communications. In such a system, each user's chip s...
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...