Sciweavers

253 search results - page 34 / 51
» Event-driven processor power management
Sort
View
ICS
2005
Tsinghua U.
15 years 11 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
ISPASS
2009
IEEE
16 years 21 days ago
User- and process-driven dynamic voltage and frequency scaling
We describe and evaluate two new, independently-applicable power reduction techniques for power management on processors that support dynamic voltage and frequency scaling (DVFS):...
Bin Lin, Arindam Mallik, Peter A. Dinda, Gokhan Me...
HPDC
2010
IEEE
15 years 6 months ago
A GPU accelerated storage system
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
Abdullah Gharaibeh, Samer Al-Kiswany, Sathish Gopa...
SECURWARE
2008
IEEE
16 years 8 days ago
Enhancing Trusted Platform Modules with Hardware-Based Virtualization Techniques
—We present the design of a trusted platform module (TPM) that supports hardware-based virtualization techniques. Our approach enables multiple virtual machines to use the comple...
Frederic Stumpf, Claudia Eckert
ISQED
2006
IEEE
94views Hardware» more  ISQED 2006»
15 years 12 months ago
System-Level SRAM Yield Enhancement
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park...