Sciweavers

14854 search results - page 2801 / 2971
» Evaluation of teleconsultation systems
Sort
View
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 10 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
PLILP
1997
Springer
15 years 10 months ago
DrScheme: A Pedagogic Programming Environment for Scheme
Abstract. Teaching introductory computing courses with Scheme elevates the intellectual level of the course and thus makes the subject more appealing to students with scienti c int...
Robert Bruce Findler, Cormac Flanagan, Matthew Fla...
SC
1992
ACM
15 years 10 months ago
Willow: A Scalable Shared Memory Multiprocessor
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
John K. Bennett, Sandhya Dwarkadas, Jay A. Greenwo...
ASPLOS
1989
ACM
15 years 10 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Software Performance Estimation in MPSoC Design
- Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-...
Márcio Oyamada, Flávio Rech Wagner, ...
« Prev « First page 2801 / 2971 Last » Next »