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CCS
2011
ACM
14 years 6 months ago
MIDeA: a multi-parallel intrusion detection architecture
Network intrusion detection systems are faced with the challenge of identifying diverse attacks, in extremely high speed networks. For this reason, they must operate at multi-Giga...
Giorgos Vasiliadis, Michalis Polychronakis, Sotiri...
HPCA
2006
IEEE
16 years 6 months ago
InfoShield: a security architecture for protecting information usage in memory
Cyber theft is a serious threat to Internet security. It is one of the major security concerns by both network service providers and Internet users. Though sensitive information c...
Guofei Gu, Hsien-Hsin S. Lee, Joshua B. Fryman, Ju...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 11 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
ICECCS
2002
IEEE
93views Hardware» more  ICECCS 2002»
15 years 11 months ago
Mnemosyne: Designing and Implementing Network Short-Term Memory
Network traffic logs play an important role in incident analysis. With the increasing throughput of network links, maintaining a complete log of all network activity has become a...
Giovanni Vigna, Andrew Mitchel
IEEEPACT
1999
IEEE
15 years 10 months ago
A Multithreaded Java Microcontroller for Thread-Oriented Real-Time Event Handling
We propose a multithreaded Java microcontroller-called Komodo microcontroller--with a new hardware event handling mechanism that allows handling of simultaneous overlapping events...
Uwe Brinkschulte, C. Krakowski, Jochen Kreuzinger,...