Sciweavers

392 search results - page 56 / 79
» Evaluation of streaming aggregation on parallel hardware arc...
Sort
View
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
16 years 7 days ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
ISCA
2012
IEEE
237views Hardware» more  ISCA 2012»
13 years 8 months ago
BOOM: Enabling mobile memory based low-power server DIMMs
To address the real-time processing needs of large and growing amounts of data, modern software increasingly uses main memory as the primary data store for critical information. T...
Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar...
MICRO
2007
IEEE
167views Hardware» more  MICRO 2007»
16 years 13 days ago
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
Chang-Burm Cho, Wangyuan Zhang, Tao Li
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
16 years 24 days ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
ICPP
2009
IEEE
16 years 25 days ago
Perfomance Models for Blocked Sparse Matrix-Vector Multiplication Kernels
—Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architec...
Vasileios Karakasis, Georgios I. Goumas, Nectarios...