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NSDI
2004
15 years 7 months ago
OverQoS: An Overlay Based Architecture for Enhancing Internet QoS
This paper describes the design, implementation, and experimental evaluation of OverQoS, an overlay-based architecture for enhancing the best-effort service of today's Intern...
Lakshminarayanan Subramanian, Ion Stoica, Hari Bal...
ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
15 years 10 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
GECCO
2005
Springer
232views Optimization» more  GECCO 2005»
15 years 11 months ago
A hardware pipeline for function optimization using genetic algorithms
Genetic Algorithms (GAs) are very commonly used as function optimizers, basically due to their search capability. A number of different serial and parallel versions of GA exist. ...
Malay Kumar Pakhira, Rajat K. De
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
16 years 24 days ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
HPCA
2007
IEEE
16 years 6 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou