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CCGRID
2009
IEEE
16 years 1 months ago
Improving Parallel Write by Node-Level Request Scheduling
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa
DSD
2009
IEEE
77views Hardware» more  DSD 2009»
16 years 1 months ago
Pulse Generation for On-chip Data Transmission
Abstract—Pulse-based data transmission has been demonstrated as a power-saving and high performance alternative to level-based signalling over global distances. Key to its correc...
Simon Hollis
DSN
2009
IEEE
16 years 1 months ago
Fitness-guided path exploration in dynamic symbolic execution
Dynamic symbolic execution is a structural testing technique that systematically explores feasible paths of the program under test by running the program with different test input...
Tao Xie, Nikolai Tillmann, Jonathan de Halleux, Wo...
GLOBECOM
2009
IEEE
16 years 1 months ago
Multiple Radio Channel Assignement Utilizing Partially Overlapped Channels
— Existing channel assignment algorithms designed for multi-radio multi-channel wireless mesh networks (MRMC-WMN) mainly deal with orthogonal or nonoverlapped channels. But in re...
Mohammad Asadul Hoque, Xiaoyan Hong, Farhana Afroz
GLVLSI
2009
IEEE
155views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Buffer design and optimization for lut-based structured ASIC design styles
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu