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HPCA
2001
IEEE
16 years 7 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
MHCI
2009
Springer
16 years 1 months ago
Community Practices and Locative Media
The development of locative media applications is not simply about the physical location or social setting in which the interaction occurs, but rather about situating the media wi...
Katharine S. Willis, Keith Cheverst, Claudia Muell...
SIGCOMM
2006
ACM
16 years 16 days ago
XORs in the air: practical wireless network coding
— This paper proposes COPE, a new architecture for wireless mesh networks. In addition to forwarding packets, routers mix (i.e., code) packets from different sources to increase ...
Sachin Katti, Hariharan Rahul, Wenjun Hu, Dina Kat...
ASAP
2007
IEEE
175views Hardware» more  ASAP 2007»
15 years 8 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S...
IPSN
2005
Springer
16 years 2 days ago
Design considerations for solar energy harvesting wireless embedded systems
Abstract— Sustainable operation of battery powered wireless embedded systems (such as sensor nodes) is a key challenge, and considerable research effort has been devoted to energ...
Vijay Raghunathan, Aman Kansal, Jason Hsu, Jonatha...