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CODES
2004
IEEE
15 years 10 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
TC
2011
15 years 1 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
CGO
2011
IEEE
14 years 10 months ago
Language and compiler support for auto-tuning variable-accuracy algorithms
—Approximating ideal program outputs is a common technique for solving computationally difficult problems, for adhering to processing or timing constraints, and for performance ...
Jason Ansel, Yee Lok Wong, Cy P. Chan, Marek Olsze...
EDBT
2010
ACM
155views Database» more  EDBT 2010»
16 years 1 months ago
Reducing metadata complexity for faster table summarization
Since the visualization real estate puts stringent constraints on how much data can be presented to the users at once, table summarization is an essential tool in helping users qu...
K. Selçuk Candan, Mario Cataldi, Maria Luis...
ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
16 years 9 days ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir