1962 search results - page 73 / 393 » Evaluating System Performance in Gigabit Networks |
172
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QEST
2007
IEEE
16 years 12 days ago
2007
IEEE
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
173
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SDL
2003
15 years 7 months ago
2003
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
168
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ICDAR
2009
IEEE
16 years 27 days ago
2009
IEEE
Training a system to recognize handwritten words is a task that requires a large amount of data with their correct transcription. However, the creation of such a training set, inc...
187
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ANSS
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper presents an analytical method for the performability evaluation of a previously reported network memory server attached to a local area network. To increase the perform...
131
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WOSP
2004
ACM
15 years 11 months ago
2004
ACM
While the use of network intrusion detection systems (nIDS) is becoming pervasive, evaluating nIDS performance has been found to be challenging. The goal of this study is to deter...