1304 search results - page 216 / 261 » Evaluating Hardware Compilation Techniques |
171
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MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
162
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
184
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MSE
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...
138
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ISCA
1999
IEEE
15 years 10 months ago
1999
IEEE
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
166
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ASPLOS
1992
ACM
15 years 10 months ago
1992
ACM
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...