1304 search results - page 214 / 261 » Evaluating Hardware Compilation Techniques |
173
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
168
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TEI
2010
ACM
16 years 1 months ago
2010
ACM
In this paper, we present a new shape-based display technique for mobile phones: A rotatory deformation of the phone’s chassis, resulting in a tapering between the phone’s fro...
156
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MICRO
2009
IEEE
16 years 25 days ago
2009
IEEE
Dynamic Random Access Memory (DRAM) is used as the bulk of the main memory in most computing systems and its energy and power consumption has become a first-class design considera...
158
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SBACPAD
2007
IEEE
16 years 14 days ago
2007
IEEE
— Telemedicine, distance learning and e-commerce applications impose time constraints directly related to the efficacy of their operations. In order to offer reliability levels ...
137
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DATE
2006
IEEE
16 years 7 days ago
2006
IEEE
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performa...