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» Evaluating Hardware Compilation Techniques
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HPCA
2001
IEEE
16 years 6 months ago
Dynamic Branch Prediction with Perceptrons
This paper presents a new method for branch prediction. The key idea is to use one of the simplest possible neural networks, the perceptron as an alternative to the commonly used ...
Daniel A. Jiménez, Calvin Lin
HIPEAC
2010
Springer
16 years 3 months ago
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpos...
John Sartori, Rakesh Kumar
ICCD
2007
IEEE
120views Hardware» more  ICCD 2007»
16 years 3 months ago
Statistical timing analysis using Kernel smoothing
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwa...
ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
16 years 3 months ago
VALVE: Variable Length Value Encoder for Off-Chip Data Buses.
We propose VAriable Length Value Encoding (VALVE) technique to reduce the power consumption in the off-chip data buses. While past research has focused on encoding fixed length da...
Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, ...
ICCAD
2002
IEEE
101views Hardware» more  ICCAD 2002»
16 years 3 months ago
Frame-based dynamic voltage and frequency scaling for a MPEG decoder
This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption while maintaining a quality of service (QoS) constr...
Kihwan Choi, Karthik Dantu, Wei-Chung Cheng, Masso...