1304 search results - page 212 / 261 » Evaluating Hardware Compilation Techniques |
123
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VTS
1998
IEEE
15 years 10 months ago
1998
IEEE
An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed ...
211
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ECBS
2006
IEEE
15 years 10 months ago
2006
IEEE
Software product lines (PLs) are large, complex systems, demanding high maintainability and enhanced flexibility. Nonetheless, in the state of the art PL methods, features are sca...
175
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EIT
2008
IEEE
15 years 8 months ago
2008
IEEE
Abstract--In the decade since the concept was publicly introduced, power analysis attacks on cryptographic systems have become an increasingly studied topic in the computer securit...
144
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IJCV
2007
15 years 6 months ago
2007
Many vision applications require high-accuracy dense disparity maps in real-time and online. Due to time constraint, most real-time stereo applications rely on local winner-takes-a...
177
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ICCAD
2009
IEEE
15 years 4 months ago
2009
IEEE
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...