1304 search results - page 208 / 261 » Evaluating Hardware Compilation Techniques |
143
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ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...
170
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
The main goal of this paper is to develop deeper insights into viable placement-level optimization of routing. Two primary contributions are made. First, an experimental framework...
164
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
Emerging VLSI technologies and platforms are giving rise to systems with inherently high potential for runtime failure. Such failures range from intermittent electrical and mechan...
135
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification ...
156
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—Flash memory is a good candidate for the storage device in real-time systems due to its non-fluctuating performance, low power consumption and high shock resistance. Ho...