1304 search results - page 206 / 261 » Evaluating Hardware Compilation Techniques |
194
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CF
2009
ACM
16 years 24 days ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
191
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CGO
2006
IEEE
16 years 10 days ago
2006
IEEE
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...
166
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CF
2010
ACM
15 years 11 months ago
2010
ACM
Competitive parallel execution (CPE) is a simple yet attractive technique to improve the performance of sequential programs on multi-core and multi-processor systems. A sequential...
181
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CCS
1999
ACM
15 years 10 months ago
1999
ACM
In this paper we present a new approach for network intrusion detection based on concise speciļ¬cations that characterize normal and abnormal network packet sequences. Our speciļ...
172
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HIPEAC
2007
Springer
15 years 10 months ago
2007
Springer
Fine-grained program power behavior is useful in both evaluating power optimizations and observing power optimization opportunities. Detailed power simulation is time consuming and...