1304 search results - page 204 / 261 » Evaluating Hardware Compilation Techniques |
138
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CGO
2005
IEEE
15 years 12 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
171
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WACV
2005
IEEE
15 years 12 months ago
2005
IEEE
We address the problem of clustering of contour images from hardware tools based on string descriptions, in a comparative study of cluster combination techniques. Several clusteri...
158
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FPL
2004
Springer
15 years 11 months ago
2004
Springer
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...
162
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ICS
1999
Tsinghua U.
15 years 10 months ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
136
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CCS
1994
ACM
15 years 10 months ago
1994
ACM
The Escrowed Encryption Standard (EES) defines a US Government family of cryptographic processors, popularly known as "Clipper" chips, intended to protect unclassified g...