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» Evaluating Hardware Compilation Techniques
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MICRO
2007
IEEE
167views Hardware» more  MICRO 2007»
16 years 17 days ago
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
Chang-Burm Cho, Wangyuan Zhang, Tao Li
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
16 years 3 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
ASPLOS
2010
ACM
16 years 1 months ago
Addressing shared resource contention in multicore processors via scheduling
Contention for shared resources on multicore processors remains an unsolved problem in existing systems despite significant research efforts dedicated to this problem in the past...
Sergey Zhuravlev, Sergey Blagodurov, Alexandra Fed...
ICC
2007
IEEE
144views Communications» more  ICC 2007»
16 years 18 days ago
On Mitigating In-band Wormhole Attacks in Mobile Ad Hoc Networks
— Colluding malicious insider nodes with no special hardware capability can use packet encapsulation and tunnelling to create bogus short-cuts (in-band wormholes) in routing path...
Xu Su, Rajendra V. Boppana
ATVA
2007
Springer
136views Hardware» more  ATVA 2007»
16 years 14 days ago
Symbolic Fault Tree Analysis for Reactive Systems
Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, wh...
Marco Bozzano, Alessandro Cimatti, Francesco Tappa...