1304 search results - page 202 / 261 » Evaluating Hardware Compilation Techniques |
160
click to vote
ISLPED
2004
ACM
15 years 11 months ago
2004
ACM
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
184
click to vote
EDCC
2010
Springer
15 years 11 months ago
2010
Springer
Wireless networks are starting to be populated by interconnected devices that reveal remarkable hardware and software differences. This fact raises a number of questions on the ap...
157
click to vote
APCSAC
2000
IEEE
15 years 10 months ago
2000
IEEE
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select impl...
154
click to vote
ASPLOS
1991
ACM
15 years 9 months ago
1991
ACM
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
161
click to vote
MASCOTS
2003
15 years 7 months ago
2003
Scalability is the primary challenge to studying large complex network systems with network emulation. This paper studies topology partitioning, assigning disjoint pieces of the n...