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» Evaluating Hardware Compilation Techniques
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HPCA
2006
IEEE
16 years 6 months ago
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...
David A. Penry, Daniel Fay, David Hodgdon, Ryan We...
ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
16 years 3 months ago
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. ...
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
16 years 29 days ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
WOSP
2010
ACM
16 years 1 months ago
A general result for deriving product-form solutions in markovian models
In this paper we provide a general method to derive productform solutions for stochastic models. We take inspiration from the Reversed Compound Agent Theorem [14] and we provide a...
Andrea Marin, Maria Grazia Vigliotti
RTCSA
2009
IEEE
16 years 1 months ago
PLL Based Time Synchronization in Wireless Sensor Networks
Abstract—Time synchronization is a key component in numerous wireless sensor network applications. Most of the current software based time synchronization approaches suffer from ...
Gang Zhou, Sachin Shetty, George Simms, Min Song