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» Evaluating Hardware Compilation Techniques
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ISPD
2005
ACM
145views Hardware» more  ISPD 2005»
15 years 12 months ago
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...
Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Ya...
PACS
2004
Springer
112views Hardware» more  PACS 2004»
15 years 11 months ago
Low-Overhead Core Swapping for Thermal Management
Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature managemen...
Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita...
ISCA
2003
IEEE
144views Hardware» more  ISCA 2003»
15 years 11 months ago
Half-Price Architecture
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
Ilhyun Kim, Mikko H. Lipasti
DATE
2010
IEEE
109views Hardware» more  DATE 2010»
15 years 11 months ago
TIMBER: Time borrowing and error relaying for online timing error resilience
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram...
DATE
2010
IEEE
158views Hardware» more  DATE 2010»
15 years 11 months ago
Energy- and endurance-aware design of phase change memory caches
—Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides m...
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun,...