1304 search results - page 189 / 261 » Evaluating Hardware Compilation Techniques |
146
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HPCS
2006
IEEE
16 years 11 days ago
2006
IEEE
This paper presents the initial design of the Cyclops-64 (C64) system software infrastructure and tools under development as a joint effort between IBM T.J. Watson Research Center...
168
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SPAA
2006
ACM
16 years 8 days ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
186
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CGO
2005
IEEE
15 years 12 months ago
2005
IEEE
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
177
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ICS
1999
Tsinghua U.
15 years 10 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
187
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CASES
2005
ACM
15 years 8 months ago
2005
ACM
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...