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» Evaluating Hardware Compilation Techniques
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ICCD
2000
IEEE
75views Hardware» more  ICCD 2000»
16 years 3 months ago
Hybridizing and Coalescing Load Value Predictors
Most well-performing load value predictors are hybrids that combine multiple predictors into one. Such hybrids are often large. To reduce their size and to improve their performan...
Martin Burtscher, Benjamin G. Zorn
ATVA
2006
Springer
114views Hardware» more  ATVA 2006»
15 years 10 months ago
Selective Approaches for Solving Weak Games
Abstract. Model-checking alternating-time properties has recently attracted much interest in the verification of distributed protocols. While checking the validity of a specificati...
Malte Helmert, Robert Mattmüller, Sven Schewe
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
16 years 24 days ago
EPIC: Ending Piracy of Integrated Circuits
As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized exces...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
DSD
2007
IEEE
105views Hardware» more  DSD 2007»
16 years 20 days ago
Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment
With continuing increase in soft error rates, its foreseeable that multiple faults will eventually need to be considered when modeling circuit sensitivity and evaluating faulttole...
Christian J. Hescott, Drew C. Ness, David J. Lilja
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
16 years 12 days ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk