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CODES
2007
IEEE
16 years 21 days ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
CODES
2005
IEEE
15 years 12 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
HPCC
2009
Springer
15 years 11 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
ISCAS
2007
IEEE
90views Hardware» more  ISCAS 2007»
16 years 19 days ago
Leakage-Aware Design of Nanometer SoC
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu
CAV
2009
Springer
150views Hardware» more  CAV 2009»
16 years 6 months ago
Automated Analysis of Java Methods for Confidentiality
We address the problem of analyzing programs such as J2ME midlets for mobile devices, where a central correctness requirement concerns confidentiality of data that the user wants t...
Pavol Cerný, Rajeev Alur