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» Evaluating Hardware Compilation Techniques
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ASPDAC
1995
ACM
104views Hardware» more  ASPDAC 1995»
15 years 10 months ago
Power analysis of a 32-bit embedded microcontroller
A new approach for power analysis of microprocessorshas recently been proposed [1]. The idea is to look at the power consumption in a microprocessor from the point of view of the ...
Vivek Tiwari, Mike Tien-Chien Lee
ATS
2009
IEEE
142views Hardware» more  ATS 2009»
16 years 1 months ago
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
Stephan Eggersglüß, Daniel Tille, Rolf ...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 11 days ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
FPL
2009
Springer
96views Hardware» more  FPL 2009»
15 years 11 months ago
Noise impact of single-event upsets on an FPGA-based digital filter
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
Brian H. Pratt, Michael J. Wirthlin, Michael P. Ca...
TVCG
2012
184views Hardware» more  TVCG 2012»
13 years 8 months ago
Unified Boundary-Aware Texturing for Interactive Volume Rendering
—In this paper, we describe a novel approach for applying texture mapping to volumetric data sets. In contrast to previous approaches, the presented technique enables a unified i...
Timo Ropinski, Stefan Diepenbrock, Stefan Bruckner...