1304 search results - page 180 / 261 » Evaluating Hardware Compilation Techniques |
180
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MICRO
2007
IEEE
16 years 19 days ago
2007
IEEE
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
155
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
178
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APCCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper, we develop a robust bit-plane watermarking technique based on zerotree coding. A robust watermark is an imperceptible but indelible code that can be used for owners...
151
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ISCA
1992
IEEE
15 years 10 months ago
1992
IEEE
This paper discusses three techniques useful in relaxing the constraints imposed by control flow on parallelism: control dependence analysis, executing multiple flows of control s...
134
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ICCD
2007
IEEE
15 years 10 months ago
2007
IEEE
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...