1304 search results - page 177 / 261 » Evaluating Hardware Compilation Techniques |
143
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ISCAS
2005
IEEE
15 years 12 months ago
2005
IEEE
Abstract— In this paper, we propose a novel common subexpresson elimination (CSE) method to be used for VLSI design of multiplierless finite impulse response (FIR) filter with ...
146
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ISPDC
2003
IEEE
15 years 11 months ago
2003
IEEE
— This paper presents a new power management technique integrated into a multithreaded microcontroller with builtin real-time scheduling schemes. Power management is done by hard...
154
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IPPS
1998
IEEE
15 years 10 months ago
1998
IEEE
We propose a generalized forward recovery checkpointing scheme, with lookahead execution and rollback validation. This method takes advantage of voting and comparison on multiple v...
212
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PC
2007
15 years 5 months ago
2007
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
164
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VTS
2008
IEEE
16 years 22 days ago
2008
IEEE
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...