1304 search results - page 176 / 261 » Evaluating Hardware Compilation Techniques |
169
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RV
2010
Springer
15 years 4 months ago
2010
Springer
Software transactional memories (STMs) promise simple and efficient concurrent programming. Several correctness properties have been proposed for STMs. Based on a bounded conflict ...
147
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ICCD
2007
IEEE
15 years 10 months ago
2007
IEEE
Transaction-level modeling (TLM) allows a designer to save functional verification effort during the modular refinement of an SoC by reusing the prior implementation of a module a...
183
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ISCA
1998
IEEE
15 years 10 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
138
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IEEEARES
2008
IEEE
16 years 23 days ago
2008
IEEE
For many storage providers, the cost of providing service calls exceeds the costs of the hardware being serviced. In this paper, we show that zeromaintenance, small disk arrays ar...
151
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SPIN
2007
Springer
16 years 14 days ago
2007
Springer
Recent development in computer hardware has brought more wide-spread emergence of shared-memory, multi-core systems. These architectures offer opportunities to speed up various ta...