1304 search results - page 174 / 261 » Evaluating Hardware Compilation Techniques |
182
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SBACPAD
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper presents a theoretical study to evaluate the performance of a family of parallel implementations of the propagation algorithm. The propagation algorithm is used to an i...
163
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
144
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ICCAD
1998
IEEE
15 years 10 months ago
1998
IEEE
In this paper, we propose a high-level variable selection for partial-scan approach to improve the testability of digital systems. The testability of a design is evaluated at the ...
140
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ITC
1996
IEEE
15 years 10 months ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
162
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ISLPED
1996
ACM
15 years 10 months ago
1996
ACM
The growing demand for portable electronic devices has led to an increased emphasis on power consumption within the semiconductor industry. As a result, designers are now encourag...