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» Evaluating Hardware Compilation Techniques
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CF
2006
ACM
16 years 10 days ago
Instruction folding in a hardware-translation based java virtual machine
Bytecode hardware-translation improves the performance of a Java Virtual Machine (JVM) with small hardware resource and complexity overhead. Instruction folding is a technique to ...
Hitoshi Oi
DATE
2005
IEEE
169views Hardware» more  DATE 2005»
15 years 12 months ago
Activity Packing in FPGAs for Leakage Power Reduction
In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a ...
Hassan Hassan, Mohab Anis, Antoine El Daher, Moham...
ECBS
2005
IEEE
92views Hardware» more  ECBS 2005»
15 years 12 months ago
Towards a Systemic Approach to Autonomic Systems Engineering
An autonomic system is structured as a network of autonomic elements that collaborate to achieve the system’s purpose. This paper examines the potential benefit of using well-es...
David W. Bustard, Roy Sterritt, A. Taleb-Bendiab, ...
ISCA
2005
IEEE
87views Hardware» more  ISCA 2005»
15 years 12 months ago
A Robust Main-Memory Compression Scheme
Lossless data compression techniques can potentially free up more than 50% of the memory resources. However, previously proposed schemes suffer from high access costs. The propose...
Magnus Ekman, Per Stenström
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
15 years 11 months ago
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
Programming network processors remains an art due to the variety of different network processor architectures and due to little support to reason and explore implementations on su...
Matthias Gries, Chidamber Kulkarni, Christian Saue...