1304 search results - page 171 / 261 » Evaluating Hardware Compilation Techniques |
145
click to vote
ISCA
2006
IEEE
16 years 12 days ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
158
click to vote
MICRO
2007
IEEE
16 years 19 days ago
2007
IEEE
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in fu...
208
click to vote
ISCA
1995
IEEE
15 years 10 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
208
click to vote
ASPLOS
2011
ACM
14 years 10 months ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
164
click to vote
ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
This paper presents a generalized semi-analytic method for computing oscillator phase noise spectra, including the details very close to the oscillation frequency. The starting po...