1304 search results - page 158 / 261 » Evaluating Hardware Compilation Techniques |
148
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ISCA
1993
IEEE
15 years 10 months ago
1993
IEEE
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...
194
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LCTRTS
2007
Springer
16 years 18 days ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
188
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MICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
181
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
166
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ISCC
2000
IEEE
15 years 11 months ago
2000
IEEE
Performance modeling and evaluation techniques are essential when designing and implementing distributed software systems. Constructing performance models for such systems can req...