1304 search results - page 155 / 261 » Evaluating Hardware Compilation Techniques |
148
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ITC
1989
IEEE
15 years 10 months ago
1989
IEEE
- The electrical effects of CMOS IC physical defects that caused stuck-openfaults are evaluated, including their voltage levels, quiescent power supply current (IDDQ), transient re...
139
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RV
2010
Springer
15 years 4 months ago
2010
Springer
Execution paths expose non-functional information such as system reliability and performance, which can be collected using runtime verification techniques. Statistics gathering an...
203
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SIGMETRICS
2011
ACM
14 years 9 months ago
2011
ACM
Branch taken rate and transition rate have been proposed as metrics to characterize the branch predictability. However, these two metrics may misclassify branches with regular his...
193
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ISCA
2012
IEEE
13 years 9 months ago
2012
IEEE
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
172
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CORR
2008
Springer
15 years 6 months ago
2008
Springer
Pipelining is a well understood and often used implementation technique for increasing the performance of a hardware system. We develop several SystemC/C++ modeling techniques tha...