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» Evaluating Hardware Compilation Techniques
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ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Variability-aware robust design space exploration of chip multiprocessor architectures
Abstract— In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufactu...
Gianluca Palermo, Cristina Silvano, Vittorio Zacca...
DDECS
2008
IEEE
97views Hardware» more  DDECS 2008»
16 years 28 days ago
Incremental SAT Instance Generation for SAT-based ATPG
— Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been ...
Daniel Tille, Rolf Drechsler
DATE
2007
IEEE
90views Hardware» more  DATE 2007»
16 years 24 days ago
Bus access optimisation for FlexRay-based distributed embedded systems
FlexRay will very likely become the de-facto standard for in-vehicle communications. Its main advantage is the combination of high speed static and dynamic transmission of message...
Traian Pop, Paul Pop, Petru Eles, Zebo Peng
DSD
2006
IEEE
89views Hardware» more  DSD 2006»
16 years 16 days ago
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar
The ModEasy project seeks to develop techniques and software tools to aid in the development of reliable microprocessor based electronic (embedded) systems using advanced developm...
Sébastien Le Beux, Philippe Marquet, Ouassi...
ICCAD
1998
IEEE
117views Hardware» more  ICCAD 1998»
15 years 10 months ago
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
Junwei Hou, Abhijit Chatterjee