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» Evaluating Hardware Compilation Techniques
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CHARME
2001
Springer
107views Hardware» more  CHARME 2001»
15 years 10 months ago
Using Combinatorial Optimization Methods for Quantification Scheduling
Model checking is the process of verifying whether a model of a concurrent system satisfies a specified temporal property. Symbolic algorithms based on Binary Decision Diagrams (BD...
Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, Jame...
ASPDAC
2005
ACM
99views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Implication of assertion graphs in GSTE
- We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal v...
Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu S...
CCS
2011
ACM
14 years 6 months ago
VMCrypt: modular software architecture for scalable secure computation
Garbled circuits play a key role in secure computation. Unlike previous work, which focused mainly on efficiency and automation aspects of secure computation, in this paper we foc...
Lior Malka
ICCD
2000
IEEE
69views Hardware» more  ICCD 2000»
15 years 11 months ago
Hierarchical Simulation of a Multiprocessor Architecture
When proposing new architectural enhancements, it is also important to account for the hardware complexity. To achieve this goal, we propose to model the new design in a hardware ...
Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra
CAV
2008
Springer
125views Hardware» more  CAV 2008»
15 years 8 months ago
A Practical Approach to Word Level Model Checking of Industrial Netlists
In this paper we present a word-level model checking method that attempts to speed up safety property checking of industrial netlists. Our aim is to construct an algorithm that all...
Per Bjesse