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» Evaluating Hardware Compilation Techniques
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CAV
2004
Springer
87views Hardware» more  CAV 2004»
15 years 12 months ago
GSTE Is Partitioned Model Checking
Verifying whether an ω-regular property is satisfied by a finite-state system is a core problem in model checking. Standard techniques build an automaton with the complementary ...
Roberto Sebastiani, Eli Singerman, Stefano Tonetta...
CODES
2008
IEEE
16 years 28 days ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
16 years 3 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
AHS
2007
IEEE
262views Hardware» more  AHS 2007»
16 years 24 days ago
Addressing the Metric Challenge: Evolved versus Traditional Fault Tolerant Circuits
The field of Evolvable Hardware, applying artificial evolution to the design of digital and analogue hardware is around ten years old. However, the field is far from reaching m...
Pauline C. Haddow, Morten Hartmann, Asbjørn...
GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
16 years 15 days ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...