1304 search results - page 140 / 261 » Evaluating Hardware Compilation Techniques |
186
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ISSS
1997
IEEE
15 years 10 months ago
1997
IEEE
Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application-specific requirements. We present an analytical strategy for explo...
157
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ICCD
2002
IEEE
16 years 3 months ago
2002
IEEE
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for...
133
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Hardware-timestamping is essential for achieving tight synchronization in networking applications. This mechanism is selectively used on few high-cost tailored systems. Actual μP...
181
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DATE
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
169
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ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation....