1304 search results - page 139 / 261 » Evaluating Hardware Compilation Techniques |
147
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MICRO
2008
IEEE
16 years 25 days ago
2008
IEEE
—Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Par...
193
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ISQED
2006
IEEE
16 years 14 days ago
2006
IEEE
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
136
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ICCAD
1995
IEEE
15 years 10 months ago
1995
IEEE
This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding...
219
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MICRO
1995
IEEE
15 years 10 months ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
153
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SAT
2010
Springer
15 years 4 months ago
2010
Springer
Previous work has shown that circuit representations can be exploited in QBF solvers to obtain useful performance improvements. In this paper we examine some additional techniques ...