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» Evaluating Hardware Compilation Techniques
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IEEEPACT
2005
IEEE
16 years 1 days ago
Instruction Based Memory Distance Analysis and its Application
Feedback-directed Optimization has become an increasingly important tool in designing and building optimizing compilers as itprovides a means to analyze complexprogram behavior th...
Changpeng Fang, Steve Carr, Soner Önder, Zhen...
ISCA
1995
IEEE
92views Hardware» more  ISCA 1995»
15 years 10 months ago
A Comparison of Full and Partial Predicated Execution Support for ILP Processors
One can e ectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential bene ts of predicated execution are hig...
Scott A. Mahlke, Richard E. Hank, James E. McCormi...
DAC
2004
ACM
16 years 7 months ago
STAC: statistical timing analysis with correlation
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
Jiayong Le, Xin Li, Lawrence T. Pileggi
CC
2009
Springer
116views System Software» more  CC 2009»
16 years 7 months ago
A Framework for Exploring Optimization Properties
Important challenges for compiler optimization include determining what optimizations to apply, where to apply them and what is a good sequence in which to apply them. To address t...
Min Zhao, Bruce R. Childers, Mary Lou Soffa
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 7 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...