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VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
16 years 16 days ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ISLPED
2004
ACM
169views Hardware» more  ISLPED 2004»
15 years 11 months ago
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
Deming Chen, Jason Cong
DSN
2002
IEEE
15 years 11 months ago
32-Bit Cyclic Redundancy Codes for Internet Applications
Standardized 32-bit Cyclic Redundancy Codes provide fewer bits of guaranteed error detection than they could, achieving a Hamming Distance (HD) of only 4 for maximum-length Ethern...
Philip Koopman
ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
15 years 11 months ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
CHI
2000
ACM
15 years 10 months ago
HandSCAPE: a vectorizing tape measure for on-site measuring applications
We introduce HandSCAPE, an orientation-aware digital tape measure, as an input device for digitizing field measurements, and visualizing the volume of the resulting vectors with c...
Jay Lee, Victor Su, Sandia Ren, Hiroshi Ishii