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VLDB
1997
ACM
126views Database» more  VLDB 1997»
15 years 10 months ago
Dynamic Memory Adjustment for External Mergesort
Sorting is a memory intensive operation whose performance is greatly affected by the amount of memory available as work space. When the input size is unknown or available memory s...
Weiye Zhang, Per-Åke Larson
ARITH
1993
IEEE
15 years 10 months ago
Fast implementations of RSA cryptography
We detail and analyse the critical techniques which may be combined in the design of fast hardware for RSA cryptography: chinese remainders, star chains, Hensel's odd divisio...
Mark Shand, Jean Vuillemin
ICCAD
1993
IEEE
123views Hardware» more  ICCAD 1993»
15 years 10 months ago
Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...
Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 10 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
DAC
1994
ACM
15 years 10 months ago
Exact Minimum Cycle Times for Finite State Machines
In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though th...
William K. C. Lam, Robert K. Brayton, Alberto L. S...
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