Sciweavers

19383 search results - page 3625 / 3877
» Estimating the
Sort
View
ISPASS
2006
IEEE
16 years 20 days ago
Simulation sampling with live-points
Current simulation-sampling techniques construct accurate model state for each measurement by continuously warming large microarchitectural structures (e.g., caches and the branch...
Thomas F. Wenisch, Roland E. Wunderlich, Babak Fal...
IV
2006
IEEE
104views Visualization» more  IV 2006»
16 years 20 days ago
Easy Grocery: 3D Visualization in e-Grocery
There are many deficiencies in the traditional electronic commerce schema. The main problem for consideration is the text and picture based design that underpins current HTML syst...
J. Somerville, Liz J. Stuart, N. Barlow
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 20 days ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
MICRO
2006
IEEE
100views Hardware» more  MICRO 2006»
16 years 20 days ago
Serialization-Aware Mini-Graphs: Performance with Fewer Resources
Instruction aggregation—the grouping of multiple operations into a single processing unit—is a technique that has recently been used to amplify the bandwidth and capacity of c...
Anne Bracy, Amir Roth
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
16 years 20 days ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
« Prev « First page 3625 / 3877 Last » Next »