19383 search results - page 3613 / 3877 » Estimating the |
163
click to vote
ISPASS
2007
IEEE
16 years 28 days ago
2007
IEEE
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
189
click to vote
ISQED
2007
IEEE
16 years 28 days ago
2007
IEEE
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
196
click to vote
KBSE
2007
IEEE
16 years 28 days ago
2007
IEEE
Software developers spend a significant portion of their resources handling user-submitted bug reports. For software that is widely deployed, the number of bug reports typically ...
179
click to vote
MICRO
2007
IEEE
16 years 28 days ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
205
click to vote
MICRO
2007
IEEE
16 years 28 days ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...