5623 search results - page 953 / 1125 » Estimating in Actual Time |
155
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DAC
1999
ACM
16 years 7 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
165
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
141
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
196
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
178
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...