6289 search results - page 429 / 1258 » Error Sequence Analysis |
194
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RTS
2006
15 years 6 months ago
2006
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
160
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ICIP
2003
IEEE
16 years 8 months ago
2003
IEEE
The binary Distortion Compensated Dither-Modulation (DCDM), which can be regarded to as a baseline for quantizationbased data-hiding methods, is rigorously analyzed. A novel and a...
160
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
Abstract— In bounded model checking (BMC)-based verification flows lack of reachability constraints often leads to false negatives. At present, it is daily practice of a veri...
184
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FMICS
2009
Springer
16 years 1 months ago
2009
Springer
Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve nondeterminism, which in turn, poses a challenge to th...
196
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IWCMC
2009
ACM
16 years 1 months ago
2009
ACM
We derive theoretical bit and frame error rate expressions for decode-and-forward (DF) collaborative networks containing M users, employing a variety of block codes over a Rayleig...