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ISQED
2008
IEEE
85views Hardware» more  ISQED 2008»
16 years 1 months ago
A Statistic-Based Approach to Testability Analysis
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulati...
Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen
DATE
2006
IEEE
121views Hardware» more  DATE 2006»
16 years 22 days ago
Analysis of the impact of bus implemented EDCs on on-chip SSN
In this paper we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN...
Daniele Rossi, Carlo Steiner, Cecilia Metra
ICC
2000
IEEE
119views Communications» more  ICC 2000»
15 years 11 months ago
Analysis of Multilevel-Quantized Soft-Limiting Detector for an FH-SSMA System
Abstract: In this paper, a multilevel-quantized soft- limiting (SL-MQ) detector for frequency hopping spread spectrum multiple access (FH-SSMA) system is proposed and analyzed. Num...
Jian F. Weng, Guo Q. Xue, Tho Le-Ngoc, Sofiè...
ECBS
1997
IEEE
144views Hardware» more  ECBS 1997»
15 years 11 months ago
An analysis of the Ariane 5 flight 501 failure-a system engineering perspective
The report issued by the Inquiry Board in charge of inspecting the Ariane 5 flight 501 failure concludes that causes of the failure are rooted into poor S/W Engineering practice. ...
Gérard Le Lann
ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
15 years 10 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...