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DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 11 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
DATE
2000
IEEE
128views Hardware» more  DATE 2000»
15 years 11 months ago
A Bus Delay Reduction Technique Considering Crosstalk
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem f...
Kei Hirose, Hiroto Yasuura
DCC
2000
IEEE
15 years 11 months ago
Lossless Compression of High-Volume Numerical Data from Simulations
Applications in scientific computing operate with high-volume numerical data and the occupied space should be reduced. Traditional compression algorithms cannot provide sufficie...
Vadim Engelson, Dag Fritzson, Peter Fritzson
ICRA
2000
IEEE
186views Robotics» more  ICRA 2000»
15 years 11 months ago
3D Motion Tracking of a Mobile Robot in a Natural Environment
This paper presents a vision-based tracking system suitable for autonomous robot vehicle guidance. The system includes a head with three on-board CCD cameras, which can be mounted...
Parvaneh Saeedi, Peter D. Lawrence, David G. Lowe
IJCNN
2000
IEEE
15 years 11 months ago
Hardware Implementation of a PCA Learning Network by an Asynchronous PDM Digital Circuit
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...
Yuzo Hirai, Kuninori Nishizawa